An experimental 640-Gbit/s ATM switching system is described. The switching system is scalable and quasi-non-blocking and uses hardware self-rearrangement in a three-stage network. Hardware implementation results for the switching system are presented. The switching system is fabricated using advanced 0.25-µm CMOS devices, high-density multi-chip-module (MCM) technology, and optical wavelength-division-multiplexing (WDM) interconnection technology. A scalable 80-Gbit/s switching module is fabricated in combination with a developed scalable-distributed-arbitration technique, and a WDM interconnection system that connects multiple 80-Gbit/s switching modules is developed. Using these components, an experimental 640-Gbit/s switching system is partially constructed. The 640-Gbit/s switching system will be applied to future broadband ATM networks.

A multi-domain GMPLS layer-2 switch capable network with VLAN tag swapping is demonstrated for the first time. In this demonstration, we verify three new features, establishing path with designating VLAN IDs, swapping VLAN ID on prototype switch, and management of VLAN IDs per domain. Using those three features, carrier-class Ethernet backbone networks which supports path route designation in multi-domain network can be established.

Frame loss of the optical layer protection switching using Plumbum Lanthanum Zirconium Titanium (PLZT) optical switch is evaluated. Experimental results show that typically 62 µs guard time is required for commercially available non-burst mode 10 Gigabit Ethernet modules.

The rapid development of Asynchronous Transfer Mode technology in the last 10-15 years has stimulated renewed interest in the design and analysis of switching systems, leading to new ideas for system designs and new insights into the performance and evaluation of such systems. As ATM moves closer to realizing the vision of ubiquitous broadband ISDN services, the design of switching systems takes on growing importance. This paper seeks to clarify the key architectural issues for ATM switching system design and provides a survey of the current state-of-the-art.

A wavelength path (WP) network management scheme is proposed for a photonic network. Multimedia data streams are integrated into a single-mode fiber using wave-length division WP multiplexing; both analog/digital and STM/ATM communications are handled. The WP management scheme using WP blocks (WPBs) with guard bands is described. An initially assigned WP does not use the guard band and most bandwidth changes made to accommodate WP changes occur within the original WPB using the guard band. An effective WP assignment method based on a recursive packing scheme is also proposed. The proposed WP packing scheme with guard band realizes a maximum network efficiency of 98%, and the probability of WP reassignment is under 10%. The techniques introduced in this paper permit the realization of flexible and effective multimedia services with a multimedia photonic network.

This paper proposes a 3-stage ATM switch architecture that uses optical WDM (wavelength division multiplexing) grouped links and dynamic bandwidth sharing. The proposed architecture has two features. The first is the use of WDM technology which makes the number of cables used in the system proportional to system size. The second is the use of dynamic bandwidth sharing among WDM grouped links. This prevents the statistical multiplexing gain offered by WDM from falling even if switching system becomes large. A performance evaluation confirms the scaleability and cost-effectiveness of the proposed architecture. It is scaleable in terms of the number of cables and admissible load. We show how the appropriate wavelength signal speed can be determined to implement the switch in a cost-effective manner. Therefore, the proposed architecture will suit future high-speed multimedia ATM networks.

This paper proposes a new high-speed network architecture called Dynamic Transfer Mode, DTM. At the entrance of the DTM network, destination addresses such as IP addresses are converted into DTM routing information and attached to the packet header. In a DTM network, a connection is set up on-the-fly by sending a series of routing link identifiers to the destination, so burst data transfers like WWW traffic are efficiently carried. A connection between adjacent nodes is created and released dynamically within the burst transfer period. This yields higher statistical multiplexing gain and improved bandwidth efficiency compared to with conventional STM. Time division multiplexing is utilized so delay jitter or cell loss, the major drawbacks of Asynchronous Transfer Mode, are avoided. This paper analyzes the performance of a DTM network and describes an implemented switching system. Because a DTM network uses source-routing and passive STM switching, it simplifies the core transit switch while localizing intelligence to edge nodes. A simplified core transit switch is well suited for future high-speed backbone networks.

This paper proposesd a non-blocking multi-stage ATM switch based on a hierarchical-cell-resequencing (HCR) mechanism and high-speed WDM interconnection and reports on its feasibility study. In a multi-stage ATM switch, cell-based routing is effective to make the switch non-blocking, because all traffic is randomly distributed over intermediate switching stages. But due to the multi-path conditions, cells may arrive out of sequence at the output of the switching fabric. Therefore, resequencing must be performed either at each output of the final switching stage or at the output of each switching stage. The basic HCR switch performs cell resequencing in a hierarchical manner when switching cells from an input-lines to a output-line. As a result, the cell sequence in each output of the basic HCR switch is recovered. A multi-stage HCR switch is constructed by interconnecting the input-lines and output-lines of these basic HCR switches in a hierarchical manner. Therefore, the cell sequence in each final output of the switching fabric is conserved in a hierarchical manner. In this way, cell-based routing becomes possible and a multi-stage ATM switch with the HCR mechanism can achieve 100% throughput without any internal speed-up techniques. Because a large-capacity multi-stage HCR switch needs a huge number of high-speed signal interconnections, a breakthrough in compact optical interconnection technology is required. Therefore, this paper proposes a WDM interconnection system with an optical router arrayed waveguide filter (AWGF) that interconnects high-speed switch elements effectively and reports its feasibility study. In this architecture, each switch element is addressed by a unique wavelength. As a result, a switch in a previous stage can transmit a cell to any switch in the next stage by only selecting its cell transmission wavelength. To make this system feasible, we developed a wide-channel-spacing optical router AWGF and compact 10-Gbit/s optical transmitter and receiver modules with a compact high-power electroabsorption distributed feedback (EA-DFB) laser and a new bit decision circuit. Using these modules, we confirmed stable operation of the WDM interconnection. This switch architecture and WDM interconnection system should enable the development of high-speed ATM switching systems that can achieve throughput of over 1 Tbit/s.

This paper presents a high-speed CAC scheme, called PERB CAC (CAC based on Prior Estimation for Residual Bandwidth). This scheme estimates the residual bandwidth in advance by generating virtual requests for connection. When an actual new request occurs, PERB CAC can instantaneously judge if the required bandwidth is larger than the estimated residual bandwidth. PERB CAC provides very rapid response time both for statistical and deterministic bandwidth allocation services, while keeping statistical multiplexing gain for the former service. Numerical results indicate that PERB CAC provides reasonably accurate and conservative values of residual bandwidth. In addition, by using PERB CAC, both services are able to be accommodated into a single VP. VP capacity control is more relaxed than is true with conventional VP-separation management. This is another merit of PERB CAC. Therefore, PERB CAC can achieve high-speed connection set-up while utilizing network resources in a cost-effective manner.

The ATM Forum specifies several fairness criteria, thus the scheduling mechanisms should allocate enough bandwidth to each connection to achieve one of such fairness criteria. However, two fairness criteria (MCR plus equal share, maximum of MCR or Max-Min share) cannot be achieved by conventional scheduling mechanisms. In this letter, we have developed new scheduling mechanisms that achieve these fairness criteria. We also present simulation results to show that our mechanisms can allocate bandwidth fairly.

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.

A new adaptive rate control with congestion prediction is developed that is highly robust against long propagation delays. It minimizes the network performance degradation caused by the delay based on prediction by extrapolating past data and correction using new notification. The simulation results show that our proposed control maintains high throughput and a smaller buffer even in long propagation delay networks, like ATM-WAN.

This paper describes a distributed traffic control scheme for large multi-stage ATM switching systems. When a new virtual circuit is to be added from some source line-interface unit (LU) to a destination LU, the system must find an optimal path through the system to accommodate the new circuit. Conventional systems have a central control processor and control lines to manage the bandwidth of all the links in the systems. The central control processor handles all the virtual circuits, but have trouble doing this when the switching system becomes large because of the limited ability of the central processor to handle the number of virtual circuits. A large switching system with Tbit/s-class throughput requires a distributed traffic control scheme. In our proposed switching system, each port of the basic switches has its own traffic monitor. Operation, administration, and maintenance (OAM) cells that are defined inside the system carry the path-congestion information to the LUs, enabling each LU to route new virtual circuits independently. A central control processor and control lines are not required. The performance of the proposed system depends on the interval between OAM cells. This paper shows how an optimal interval can be determined in order to maximize the bandwidth for user cells. This traffic control scheme will suit future Tbit/s ATM switching systems.

The effectiveness of traffic shaping for VBR traffic is analyzed. Evaluation results prove that traffic shaping can improve link efficiency for most forms of bursty VBR traffic and that link efficiency gains of more than 250% can be expected without the shaping delay imposing any significant QOS deterioration. Traffic shaping increases the link efficiency to about 80% for traffic with short burst repetition periods. The traffic shaping techniques and analytical results described herein can be employed in the traffic management of future B-ISDN/ATM networks.

This paper proposes a compact high-speed ATM switching architecture that employs a novel arbitration method. The NN matrix shaped crosspoint switch is realized with D small switch blocks (SSBs). The number of crosspoints and address comparators is reduced from N2 to (N/D)2. Each block contains N/D input lines and N/D output lines. The association between output lines and output ports is logically changed each cell period. This arrangement permits each input port to be connected to N/D output ports in each cell period. Output-line contention control is realized block-by-block so high-speed operation is realized. The traffic characteristics of the proposed switch architecture are analyzed using computer simulations. According to the simulation results, the cell loss rate of 10-8 is achieved with only 100-cell input and output-buffers under the heavy random load of 0.9 for any size switch. The proposed ATM switching architecture can construct the Gbit/s high-speed ATM switch fabric needed for B-ISDN.

The Internet is an extremely convenient network and has become one of the key infrastructures for daily life. However, it suffers from three serious problems; its structure does not suit traffic centralization, its power consumption is rapidly increasing, and its round-trip time (RTT) and delay jitter are large. This paper proposes an extremely energy efficient layer-3 network architecture for the future Internet. It combines the Service Cloud with the Cloud Router and application servers, with the Optical Aggregation Network realized by optical circuit switches, wavelength-converters, and wavelength-multiplexers/demultiplexers. User IP packets are aggregated and transferred through the Optical Aggregation Network to Cloud transparently. The proposed network scheme realizes a network structure well suited to traffic centralization, reduces the power consumption to 1/20-1/30 compared to the existing Internet, reduces the RTT and delay jitter due to its simplicity, and offers easy migration from the existing Internet.

Although the Internet is playing an increasingly significant role in global communication, it remains vulnerable to malicious traffic such as worms and DoS/DDoS attacks. In the last few years, the emergence of high speed active worms, such as Code Red II, Nimda, SQL Slammer and MS Blaster, has become a serious issue. These worms cause serious damage to communication networks throughout the world by using up network bandwidth. In addition, since conventional firewall systems are located just in front of the server and do not prevent malicious traffic from entering the network, they cannot prevent such network congestion. Therefore, the firewall between domains or between core routers should play important roles in the photonic networks. We have developed a prototype system of a network firewall using reconfigurable processors. In this paper, we overview the developed system and present its evaluation results.

A new simple cell spacing architecture that guarantees the peak cell interval and realizes preferential contention resolution is proposed. Scheduling the cell emission on departure of the previous cell, not arrival, allows the source peak cell interval to be regenerated without clumping. Priority control is also realized in the proposed spacer. A connection is scheduled either at the head or tail of the contention chain depending on its priority. The proposed method is applied to realize the UPC function. The proposed cell spacer eliminates the clumping effects of CDV completely and achieves high bandwidth efficiency.

This letter presents SAM, a multiplexer for ATM's circuit emulation services that can precisely control the cell clumping at the connection-level. Compared with a FIFO (First In First Out) multiplexer, it also improves the connection-level diffusion and CDV (Cell Delay Variation) performance. SAM can therefore significantly increase the number of connections accepted by CAC (Call Admission Control) procedures in the subsequent multiplexer.